Invited Talk - Prof. Rodolfo Pellizzoni, University of Waterloo, Canada

Abstract

Implementing safety-critical real-time systems on multicore platforms poses significant challenges. Multicore systems typically comprise a large number of shared physical resources over the memory hierarchy, such as caches, interconnections, DRAM channels, etc. Contention for access to such shared resources can significantly affect the performance of concurrent applications, making it difficult to independently verify/certify software partitions running on different cores.

In this talk, we provide an overview of OS-level memory partitioning schemes that can improve timing isolation for concurrent real-time partitions. We then focus our attention on DRAM main memory, as we often found it to be the main source of contention. We show that even when partitioning schemes are applied, worst-case access latency bounds can be extremely pessimistic due to the unfair arbitration algorithms used by commercial-off-the-shelf memory controllers. Hence, we discuss hardware and software solutions to obtain improved, guaranteed performance for real-time applications. 

Bio

Rodolfo Pellizzoni is Associate Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He received his Master degree from Scuola Superiore Sant'Anna in 2005 and his PhD from the University of Illinois at Urbana-Champaign in 2010. Rodolfo's main research interests are in real-time systems and timing analysis, with a particular focus on hardware/software architectures for timing predictability and safety certification.